Split the list scheduler into top-down and bottom-up pieces. The priority

function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26552 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f011281fa9..3506601704 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -76,6 +76,8 @@ namespace {
                  "except using generic latency"),
       clEnumValN(listSchedulingBURR, "list-burr",
                  "Bottom up register reduction list scheduling"),
+      clEnumValN(listSchedulingG5, "list-g5",
+                 "Scheduling for the PowerPC G5"),
       clEnumValEnd));
 } // namespace
 
@@ -2470,6 +2472,10 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
     break;
   case listSchedulingBURR:
     SL = createBURRListDAGScheduler(DAG, BB);
+    break;
+  case listSchedulingG5:
+    SL = createTDG5ListDAGScheduler(DAG, BB);
+    break;
   }
   BB = SL->Run();
   delete SL;