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author | Duncan Sands <baldrick@free.fr> | 2008-06-17 03:24:13 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2008-06-17 03:24:13 +0000 |
commit | a47c6c37034f4e57bc8187e959da4eadb6e24afa (patch) | |
tree | 256521a2841576b68dd9956ba2628dac1f6a1d2b /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
parent | 851bc0453350254cd45a91b6af9592003562d707 (diff) |
Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52381 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index a55f904b21..50799d10ed 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4283,7 +4283,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Copy the output from the appropriate register. Find a register that // we can use. if (OpInfo.AssignedRegs.Regs.empty()) { - cerr << "Couldn't allocate output reg for contraint '" + cerr << "Couldn't allocate output reg for constraint '" << OpInfo.ConstraintCode << "'!\n"; exit(1); } |