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author | Andrew Lenharth <andrewl@lenharth.org> | 2008-02-16 01:24:58 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-02-16 01:24:58 +0000 |
commit | 22c5c1b2dfcb1da6a7ebfebea903401fc77d56e6 (patch) | |
tree | 2e65d654e3f499c5538ca7ef024a0c7c76f9d3f4 /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
parent | 527c250a9080a5b6cf0053a6215037c3769ff4a0 (diff) |
llvm.memory.barrier, and impl for x86 and alpha
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index b3d7fbfcf9..7b01d63903 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3046,6 +3046,15 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); return 0; } + case Intrinsic::memory_barrier: { + SDOperand Ops[6]; + Ops[0] = getRoot(); + for (int x = 1; x < 6; ++x) + Ops[x] = getValue(I.getOperand(x)); + + DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); + return 0; + } } } |