Implement the sadd_with_overflow intrinsic. This is converted into

"ISD::ADDO". ISD::ADDO is lowered into a target-independent form that does the
addition and then checks if the result is less than one of the operands. (If it
is, then there was an overflow.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59779 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 25 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 0469f3a23c..da62b6deb5 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4092,6 +4092,31 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
     return 0;
   }
+
+  case Intrinsic::sadd_with_overflow: {
+    // Convert to "ISD::ADDO" instruction.
+    SDValue Chain = getRoot();
+    SDValue Op1 = getValue(I.getOperand(1));
+    SDValue Op2 = getValue(I.getOperand(2));
+    MVT Ty = Op1.getValueType();
+
+    MVT ValueVTs[] = { Ty, MVT::i1, MVT::Other };
+    SDValue Ops[] = { Op1, Op2, Chain };
+
+    SDValue Result = DAG.getNode(ISD::ADDO, DAG.getVTList(&ValueVTs[0], 3),
+                                 &Ops[0], 3);
+
+    setValue(&I, Result);
+
+    unsigned NumArgRegs = Result.getNode()->getNumValues() - 1;
+    DAG.setRoot(SDValue(Result.getNode(), NumArgRegs));
+    return 0;
+  }
+  case Intrinsic::uadd_with_overflow: {
+    // TODO: Convert to "ISD::ADDC" instruction.
+    return 0;
+  }
+
   case Intrinsic::prefetch: {
     SDValue Ops[4];
     Ops[0] = getRoot();