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authorChris Lattner <sabre@nondot.org>2005-04-13 02:58:13 +0000
committerChris Lattner <sabre@nondot.org>2005-04-13 02:58:13 +0000
commite666fcfbdd1c2a8f47c4577ef4ff4a8280099e28 (patch)
tree4fafeb6fe8c239e155ed0e89cdd6cbf2f97499f9 /lib/CodeGen/SelectionDAG/SelectionDAG.cpp
parent8a8dbfa57cb8bf6bf98a5cfc434dff4d9bdf5e0b (diff)
add back the optimization that Nate added for shl X, (zext_inreg y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21273 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp25
1 files changed, 23 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index dc862b38be..48e0f7bc9a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -943,8 +943,18 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SHL:
case ISD::SRL:
case ISD::SRA:
- if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG)
+ if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+ cast<MVTSDNode>(N2)->getExtraValueType() != MVT::i1)
return getNode(Opcode, VT, N1, N2.getOperand(0));
+ else if (N2.getOpcode() == ISD::AND)
+ if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) {
+ // If the and is only masking out bits that cannot effect the shift,
+ // eliminate the and.
+ unsigned NumBits = MVT::getSizeInBits(VT);
+ if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
+ return getNode(Opcode, VT, N1, N2.getOperand(0));
+ }
+
break;
}
@@ -1040,8 +1050,19 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SRA_PARTS:
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
- if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG)
+ if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+ cast<MVTSDNode>(N3)->getExtraValueType() != MVT::i1)
return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
+ else if (N3.getOpcode() == ISD::AND)
+ if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
+ // If the and is only masking out bits that cannot effect the shift,
+ // eliminate the and.
+ unsigned NumBits = MVT::getSizeInBits(VT)*2;
+ if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
+ return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
+ }
+
+
break;
}