diff options
| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-08-13 20:31:45 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-08-13 20:31:45 +0000 |
| commit | 5cbba0167165c61deb8f3223143643083013f046 (patch) | |
| tree | b6254682cf1c9fd5dba4b6b5b30be90d92aa97cf /lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | 9a0f436da2daf8c53570d9fc06046d493e835a8f (diff) | |
Fix PR 10635. When generating integer constants, the constant element type may
be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137562 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 8b353a28b6..ab6af1b4d1 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -928,6 +928,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) { assert(Val.getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); + // In some cases the vector type is legal but the element type is illegal. + // In this case, promote the inserted value. The type does not need to match + // the vector element type. Any extra bits introduced will be + // truncated away. + if (VT.isVector()) + EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT); + unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); |