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authorJeff Cohen <jeffc@jolt-lang.org>2005-07-27 06:12:32 +0000
committerJeff Cohen <jeffc@jolt-lang.org>2005-07-27 06:12:32 +0000
commit00b16889ab461b7ecef1c91ade101186b7f1fce2 (patch)
tree263acb2b05b59235d77bee1d38fa842f2044ec0e /lib/CodeGen/SelectionDAG/SelectionDAG.cpp
parent54eed36da595f09c46a46b2b0b15757ea486b4c1 (diff)
Eliminate all remaining tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 91fbf98ab5..530422dacb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1212,7 +1212,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
break;
case ISD::SUB:
if (N1.getOpcode() == ISD::ADD) {
- if (N1.Val->getOperand(0) == N2 &&
+ if (N1.Val->getOperand(0) == N2 &&
!MVT::isFloatingPoint(N2.getValueType()))
return N1.Val->getOperand(1); // (A+B)-A == B
if (N1.Val->getOperand(1) == N2 &&
@@ -1233,7 +1233,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG)
if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT)
return N1;
-
+
// If we are sign extending a sextload, return just the load.
if (N1.getOpcode() == ISD::SEXTLOAD)
if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT)
@@ -1311,7 +1311,7 @@ void SDNode::setAdjCallChain(SDOperand N) {
SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
- SDOperand Chain, SDOperand Ptr,
+ SDOperand Chain, SDOperand Ptr,
SDOperand SV) {
SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))];
if (N) return SDOperand(N, 0);
@@ -1457,7 +1457,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
}
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
- SDOperand N1, SDOperand N2, SDOperand N3,
+ SDOperand N1, SDOperand N2, SDOperand N3,
SDOperand N4) {
std::vector<SDOperand> Ops;
Ops.reserve(4);