Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor

some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 7 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 9d32d9afac..91a8294e1d 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -193,15 +193,17 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
   }
 
   SU->Latency = 0;
-  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
+  bool SawMachineOpcode = false;
+  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
     if (N->isMachineOpcode()) {
-      unsigned SchedClass = TII->get(N->getMachineOpcode()).getSchedClass();
-      const InstrStage *S = InstrItins.begin(SchedClass);
-      const InstrStage *E = InstrItins.end(SchedClass);
-      for (; S != E; ++S)
-        SU->Latency += S->Cycles;
+      SawMachineOpcode = true;
+      SU->Latency +=
+        InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
     }
-  }
+
+  // Ensure that CopyToReg and similar nodes have a non-zero latency.
+  if (!SawMachineOpcode)
+    SU->Latency = 1;
 }
 
 /// CountResults - The results of target nodes have register or immediate