diff options
| author | Bill Wendling <isanbard@gmail.com> | 2009-04-28 01:04:53 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2009-04-28 01:04:53 +0000 |
| commit | c69d56f1154342a57c9bdd4c17a10333e3520127 (patch) | |
| tree | 4793b96fe50eeb1b430040579bb4e2c61479942b /lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | 2e9d5f912a9841d3685ba0241abe1131943fed29 (diff) | |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index aecd02aba3..20a081d054 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { } llvm::ScheduleDAGSDNodes * -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); |