Change the scheduler accessor methods to accept an explicit TargetMachine

argument instead of taking the SelectionDAG's TargetMachine. This is
needed for some upcoming scheduler changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59055 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 5 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index d1617bd60c..5ae3158961 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1881,27 +1881,29 @@ void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
 
 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
                                                     SelectionDAG *DAG,
+                                                    const TargetMachine *TM,
                                                     MachineBasicBlock *BB,
                                                     bool Fast) {
   if (Fast)
-    return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true,
+    return new ScheduleDAGRRList(*DAG, BB, *TM, true, true,
                                  new BURegReductionFastPriorityQueue());
 
-  const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
-  const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
+  const TargetInstrInfo *TII = TM->getInstrInfo();
+  const TargetRegisterInfo *TRI = TM->getRegisterInfo();
   
   BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
 
   ScheduleDAGRRList *SD =
-    new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ);
+    new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;  
 }
 
 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
                                                     SelectionDAG *DAG,
+                                                    const TargetMachine *TM,
                                                     MachineBasicBlock *BB,
                                                     bool Fast) {
-  return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast,
+  return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast,
                                new TDRegReductionPriorityQueue());
 }