Revert 127368 and 127371 for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 11 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 5e60aa04ea..f1a5a6599b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1140,19 +1140,13 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
       TRI->getMinimalPhysRegClass(Reg, VT);
     const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
 
-    // If cross copy register class is the same as RC, then it must be possible
-    // copy the value directly. Do not try duplicate the def.
-    // If cross copy register class is not the same as RC, then it's possible to
-    // copy the value but it require cross register class copies and it is
-    // expensive.
-    // If cross copy register class is null, then it's not possible to copy
-    // the value at all.
+    // If cross copy register class is null, then it must be possible copy
+    // the value directly. Do not try duplicate the def.
     SUnit *NewDef = 0;
-    if (DestRC != RC) {
+    if (DestRC)
       NewDef = CopyAndMoveSuccessors(LRDef);
-      if (!DestRC && !NewDef)
-        report_fatal_error("Can't handle live physical register dependency!");
-    }
+    else
+      DestRC = RC;
     if (!NewDef) {
       // Issue copies, these can be expensive cross register class copies.
       SmallVector<SUnit*, 2> Copies;