Create a new class, MemOperand, for describing memory references

in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.

Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.

Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 25 insertions, 3 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 84cd048037..37beff9619 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -277,15 +277,27 @@ unsigned ScheduleDAG::CountResults(SDNode *Node) {
   return N;
 }
 
-/// CountOperands  The inputs to target nodes have any actual inputs first,
-/// followed by an optional chain operand, then flag operands.  Compute the
-/// number of actual operands that  will go into the machine instr.
+/// CountOperands - The inputs to target nodes have any actual inputs first,
+/// followed by optional memory operands chain operand, then flag operands.
+/// Compute the number of actual operands that  will go into the machine istr.
 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
   unsigned N = Node->getNumOperands();
   while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
     --N;
   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
     --N; // Ignore chain if it exists.
+  while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val))
+    --N; // Ignore MemOperand nodes
+  return N;
+}
+
+/// CountMemOperands - Find the index of the last MemOperandSDNode operand
+unsigned ScheduleDAG::CountMemOperands(SDNode *Node) {
+  unsigned N = Node->getNumOperands();
+  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
+    --N;
+  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
+    --N; // Ignore chain if it exists.
   return N;
 }
 
@@ -517,6 +529,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
   
 }
 
+void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) {
+  MI->addMemOperand(MO);
+}
+
 // Returns the Register Class of a subregister
 static const TargetRegisterClass *getSubRegisterRegClass(
         const TargetRegisterClass *TRC,
@@ -674,6 +690,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
 
     unsigned NumResults = CountResults(Node);
     unsigned NodeOperands = CountOperands(Node);
+    unsigned NodeMemOperands = CountMemOperands(Node);
     unsigned NumMIOperands = NodeOperands + NumResults;
     bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
                           II.getImplicitDefs() != 0;
@@ -696,6 +713,10 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
     for (unsigned i = 0; i != NodeOperands; ++i)
       AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
 
+    // Emit all of the memory operands of this instruction
+    for (unsigned i = NodeOperands; i != NodeMemOperands; ++i)
+      AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
+
     // Commute node if it has been determined to be profitable.
     if (CommuteSet.count(Node)) {
       MachineInstr *NewMI = TII->commuteInstruction(MI);
@@ -754,6 +775,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
     case ISD::EntryToken: // fall thru
     case ISD::TokenFactor:
     case ISD::LABEL:
+    case ISD::SRCVALUE:
       break;
     case ISD::CopyToReg: {
       unsigned InReg;