diff options
author | Chris Lattner <sabre@nondot.org> | 2007-02-04 08:47:20 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2007-02-04 08:47:20 +0000 |
commit | 831e0374a7da654071279f2b1f93f52f7eeb5eae (patch) | |
tree | 6306da1f2ccf2a509170fb331d8d4334193dddf6 /lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | |
parent | 3f97eb449b08069e3370d4ba7566c60bdbf0babd (diff) |
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33879 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAG.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 33227ad4e0..d290d88615 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -269,8 +269,8 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI, /// getVR - Return the virtual register corresponding to the specified result /// of the specified node. -static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) { - std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val); +static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) { + DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val); assert(I != VRBaseMap.end() && "Node emitted out of order - late"); return I->second + Op.ResNo; } @@ -283,7 +283,7 @@ static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) { void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, const TargetInstrDescriptor *II, - std::map<SDNode*, unsigned> &VRBaseMap) { + DenseMap<SDNode*, unsigned> &VRBaseMap) { if (Op.isTargetOpcode()) { // Note that this case is redundant with the final else block, but we // include it because it is the most common and it makes the logic @@ -371,7 +371,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, /// EmitNode - Generate machine code for an node and needed dependencies. /// void ScheduleDAG::EmitNode(SDNode *Node, - std::map<SDNode*, unsigned> &VRBaseMap) { + DenseMap<SDNode*, unsigned> &VRBaseMap) { unsigned VRBase = 0; // First virtual register for node // If machine instruction @@ -595,7 +595,7 @@ void ScheduleDAG::EmitSchedule() { // Finally, emit the code for all of the scheduled instructions. - std::map<SDNode*, unsigned> VRBaseMap; + DenseMap<SDNode*, unsigned> VRBaseMap; for (unsigned i = 0, e = Sequence.size(); i != e; i++) { if (SUnit *SU = Sequence[i]) { for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) |