diff options
| author | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-11 11:14:33 +0000 |
|---|---|---|
| committer | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-11 11:14:33 +0000 |
| commit | 34525f9ac098c1c6bc9002886d6da3039a284fd2 (patch) | |
| tree | b4cb498a55dda76f1a134df25d3c587cc35b2f83 /lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | |
| parent | 7550f96b2f3a5e187f737ddad45563962fbd509c (diff) | |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index 473e1384e3..a9b6a2eca8 100644 --- a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -94,9 +94,9 @@ ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { continue; for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) { - MVT VT = ScegN->getSimpleValueType(i); + EVT VT = ScegN->getValueType(i); if (TLI->isTypeLegal(VT) - && (TLI->getRegClassFor(VT)->getID() == RCId)) { + && (TLI->getRegClassFor(VT)->getID() == RCId)) { NumberDeps++; break; } @@ -132,9 +132,9 @@ unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) { const SDValue &Op = ScegN->getOperand(i); - MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); + EVT VT = Op.getNode()->getValueType(Op.getResNo()); if (TLI->isTypeLegal(VT) - && (TLI->getRegClassFor(VT)->getID() == RCId)) { + && (TLI->getRegClassFor(VT)->getID() == RCId)) { NumberDeps++; break; } @@ -332,7 +332,7 @@ signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { // Gen estimate. for (unsigned i = 0, e = SU->getNode()->getNumValues(); i != e; ++i) { - MVT VT = SU->getNode()->getSimpleValueType(i); + EVT VT = SU->getNode()->getValueType(i); if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) && TLI->getRegClassFor(VT)->getID() == RCId) @@ -341,7 +341,7 @@ signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { // Kill estimate. for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) { const SDValue &Op = SU->getNode()->getOperand(i); - MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); + EVT VT = Op.getNode()->getValueType(Op.getResNo()); if (isa<ConstantSDNode>(Op.getNode())) continue; @@ -485,7 +485,7 @@ void ResourcePriorityQueue::scheduledNode(SUnit *SU) { if (ScegN->isMachineOpcode()) { // Estimate generated regs. for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) { - MVT VT = ScegN->getSimpleValueType(i); + EVT VT = ScegN->getValueType(i); if (TLI->isTypeLegal(VT)) { const TargetRegisterClass *RC = TLI->getRegClassFor(VT); @@ -496,7 +496,7 @@ void ResourcePriorityQueue::scheduledNode(SUnit *SU) { // Estimate killed regs. for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) { const SDValue &Op = ScegN->getOperand(i); - MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); + EVT VT = Op.getNode()->getValueType(Op.getResNo()); if (TLI->isTypeLegal(VT)) { const TargetRegisterClass *RC = TLI->getRegClassFor(VT); |