diff options
author | Duncan Sands <baldrick@free.fr> | 2008-02-27 10:18:23 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2008-02-27 10:18:23 +0000 |
commit | 4f069e6db1772a7e6cd8bfc360d819b56557badc (patch) | |
tree | ea41adb2304c6997c98d482de53a36891adc8196 /lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp | |
parent | be680dcea6858c438c6615326ae1c098ff448ae1 (diff) |
LegalizeTypes support for INSERT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47669 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp index d386feb260..72c1f484db 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp @@ -77,7 +77,7 @@ void DAGTypeLegalizer::ScalarizeResult(SDNode *N, unsigned ResNo) { case ISD::FCOS: R = ScalarizeRes_UnaryOp(N); break; case ISD::FPOWI: R = ScalarizeRes_FPOWI(N); break; case ISD::BUILD_VECTOR: R = N->getOperand(0); break; - case ISD::INSERT_VECTOR_ELT: R = N->getOperand(1); break; + case ISD::INSERT_VECTOR_ELT: R = ScalarizeRes_INSERT_VECTOR_ELT(N); break; case ISD::VECTOR_SHUFFLE: R = ScalarizeRes_VECTOR_SHUFFLE(N); break; case ISD::BIT_CONVERT: R = ScalarizeRes_BIT_CONVERT(N); break; case ISD::SELECT: R = ScalarizeRes_SELECT(N); break; @@ -120,6 +120,17 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_FPOWI(SDNode *N) { return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1)); } +SDOperand DAGTypeLegalizer::ScalarizeRes_INSERT_VECTOR_ELT(SDNode *N) { + // The value to insert may have a wider type than the vector element type, + // so be sure to truncate it to the element type if necessary. + SDOperand Op = N->getOperand(1); + MVT::ValueType EltVT = MVT::getVectorElementType(N->getValueType(0)); + if (MVT::getSizeInBits(Op.getValueType()) > MVT::getSizeInBits(EltVT)) + Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); + assert(Op.getValueType() == EltVT && "Invalid type for inserted value!"); + return Op; +} + SDOperand DAGTypeLegalizer::ScalarizeRes_VECTOR_SHUFFLE(SDNode *N) { // Figure out if the scalar is the LHS or RHS and return it. SDOperand EltNum = N->getOperand(2).getOperand(0); |