diff options
author | Duncan Sands <baldrick@free.fr> | 2008-02-27 10:18:23 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2008-02-27 10:18:23 +0000 |
commit | 4f069e6db1772a7e6cd8bfc360d819b56557badc (patch) | |
tree | ea41adb2304c6997c98d482de53a36891adc8196 /lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp | |
parent | be680dcea6858c438c6615326ae1c098ff448ae1 (diff) |
LegalizeTypes support for INSERT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47669 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp index 41501398f2..c4eb059380 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp @@ -357,6 +357,9 @@ bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) { case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break; case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break; + case ISD::INSERT_VECTOR_ELT: + Res = PromoteOperand_INSERT_VECTOR_ELT(N, OpNo); + break; case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break; @@ -591,6 +594,30 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) { return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); } +SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N, + unsigned OpNo) { + if (OpNo == 1) { + // Promote the inserted value. This is valid because the type does not + // have to match the vector element type. + + // Check that any extra bits introduced will be truncated away. + assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >= + MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) && + "Type of inserted value narrower than vector element type!"); + return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), + GetPromotedOp(N->getOperand(1)), + N->getOperand(2)); + } + + assert(OpNo == 2 && "Different operand and result vector types?"); + + // Promote the index. + SDOperand Idx = N->getOperand(2); + Idx = DAG.getZeroExtendInReg(GetPromotedOp(Idx), Idx.getValueType()); + return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), + N->getOperand(1), Idx); +} + SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) { assert(!(OpNo & 1) && "Return values should be legally typed!"); assert((N->getNumOperands() & 1) && "Wrong number of operands!"); |