Convert MaskedValueIsZero and all its users to use APInt. Also add

a SignBitIsZero function to simplify a common use case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 2 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
index 5e94d7bbb9..3d4ba7b500 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
@@ -446,8 +446,9 @@ SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
 
   // The top bits of the promoted condition are not necessarily zero, ensure
   // that the value is properly zero extended.
+  unsigned BitWidth = Cond.getValueSizeInBits();
   if (!DAG.MaskedValueIsZero(Cond, 
-                             MVT::getIntVTBitMask(Cond.getValueType())^1)) {
+                             APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
     Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
     MarkNewNodes(Cond.Val); 
   }
@@ -463,8 +464,9 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
   
   // The top bits of the promoted condition are not necessarily zero, ensure
   // that the value is properly zero extended.
+  unsigned BitWidth = Cond.getValueSizeInBits();
   if (!DAG.MaskedValueIsZero(Cond, 
-                             MVT::getIntVTBitMask(Cond.getValueType())^1)) {
+                             APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
     Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
     MarkNewNodes(Cond.Val); 
   }