diff options
author | Duncan Sands <baldrick@free.fr> | 2008-02-10 10:08:52 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2008-02-10 10:08:52 +0000 |
commit | d885dbdf9eb7a51ebb9a15a85921f27d8219997c (patch) | |
tree | abdd5cfa1ddaf7d13122ebe19d4d7913788271ad /lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp | |
parent | a900d1758003091d935c4d1fb4a41f6c47878f52 (diff) |
Add truncate and AssertZext result expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46926 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp index 9a0c37dd08..bb6a7f36a8 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp @@ -60,6 +60,8 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) { case ISD::ANY_EXTEND: ExpandResult_ANY_EXTEND(N, Lo, Hi); break; case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break; case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break; + case ISD::AssertZext: ExpandResult_AssertZext(N, Lo, Hi); break; + case ISD::TRUNCATE: ExpandResult_TRUNCATE(N, Lo, Hi); break; case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break; case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break; case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; @@ -202,6 +204,34 @@ void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N, } } +void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N, + SDOperand &Lo, SDOperand &Hi) { + GetExpandedOp(N->getOperand(0), Lo, Hi); + MVT::ValueType NVT = Lo.getValueType(); + MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + unsigned NVTBits = MVT::getSizeInBits(NVT); + unsigned EVTBits = MVT::getSizeInBits(EVT); + + if (NVTBits < EVTBits) { + Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, + DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits))); + } else { + Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); + // The high part must be zero, make it explicit. + Hi = DAG.getConstant(0, NVT); + } +} + +void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N, + SDOperand &Lo, SDOperand &Hi) { + MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); + Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), + DAG.getConstant(MVT::getSizeInBits(NVT), + TLI.getShiftAmountTy())); + Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); +} + void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // Lower the bit-convert to a store/load from the stack, then expand the load. |