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authorEli Friedman <eli.friedman@gmail.com>2008-12-17 03:35:17 +0000
committerEli Friedman <eli.friedman@gmail.com>2008-12-17 03:35:17 +0000
commit28dc98f7521933872b93156e3ebf5c9f8327b2b3 (patch)
tree13fc73e52fccdbe7506aeda590b5ebec9a32bd88 /lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
parent2d0484c02cc99e30f320dec376b102ad7a961904 (diff)
Fix for PR3225: disable a broken optimization in
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit. In terms of restoring the optimization, the best fix here isn't obvious... any ideas? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61119 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 8e864050ed..8abf1448db 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1211,6 +1211,8 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
}
}
+#if 0
+ // FIXME: This code is broken for shifts with a zero amount!
// If we know that all of the high bits of the shift amount are zero, then we
// can do this as a couple of simple shifts.
if ((KnownZero & HighBitMask) == HighBitMask) {
@@ -1232,6 +1234,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
DAG.getNode(Op2, NVT, InL, Amt2));
return true;
}
+#endif
return false;
}