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| author | Dan Gohman <gohman@apple.com> | 2008-08-20 18:09:38 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-20 18:09:38 +0000 |
| commit | 77ad79689d755c49146f534107421cb3d9703fed (patch) | |
| tree | 7a2f6f5ac87d97229f6f8eaf7c62fc21e9554a33 /lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | b7864a9e23be526f4f8cde529a57c8943c61c0c7 (diff) | |
Minor whitespace cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55070 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/FastISel.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 9ccfe0f7b0..7cb888ccb9 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -144,7 +144,7 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType, } unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, - const TargetRegisterClass* RC) { + const TargetRegisterClass* RC) { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetInstrDesc &II = TII->get(MachineInstOpcode); unsigned ResultReg = MRI.createVirtualRegister(RC); |