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authorOwen Anderson <resistor@mac.com>2008-08-28 17:47:37 +0000
committerOwen Anderson <resistor@mac.com>2008-08-28 17:47:37 +0000
commit40a468f24909792f000e3ccc1dda7a27b9c34b69 (patch)
treefb2af53aa61bca7268b17927d6d89ae6d1fde25f /lib/CodeGen/SelectionDAG/FastISel.cpp
parentf641395435ddfe2e3f0d9857fff4f6da77ee5427 (diff)
FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55476 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/FastISel.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 2dd228249b..4dbfadcd16 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -587,8 +587,8 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
- unsigned Op0, uint32_t Idx) {
+unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
+ const TargetRegisterClass* RC = MRI.getRegClass(Op0);
const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
unsigned ResultReg = createResultReg(SRC);