diff options
| author | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
| commit | 92bcd96bbcf42911a76570cc0974e513bc7f261d (patch) | |
| tree | f7aa5be2ae7bfc3418f06248d0efe73406e1648b /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 1c61990b2daa77f3444eb2b6d8157cdc805ce22f (diff) | |
When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef. add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6f940760e0..3cf7a2be6f 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3030,6 +3030,9 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { // fold (shl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; + // fold (shl undef, x) -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); // if (shl x, c) is known to be zero, return 0 if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnesValue(OpSizeInBits))) |