diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-10-17 21:24:15 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-10-17 21:24:15 +0000 |
| commit | 50662beab7cc6394a0d6524d16fe7de1d5192196 (patch) | |
| tree | c523a4a6ec2677c166127f5640dc0c85efdfd7fe /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 158cf5edb27e504f8dd4cf86d1de351e6fccc6ed (diff) | |
Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31019 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 997820dd64..aa6f4ae98c 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3689,7 +3689,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We // can only do this if the top bits are known zero. - if (TLI.MaskedValueIsZero(N1, + if (TLI.MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){ // Okay, get the un-inverted input value. SDOperand Val; |