diff options
| author | Richard Osborne <richard@xmos.com> | 2011-01-31 17:41:44 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-01-31 17:41:44 +0000 |
| commit | 4e3740ee6ddfc5895061245364de21e3f73517fe (patch) | |
| tree | f6c7135d55a72babcac2a2f2a4b920878d39cb40 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | e85dcb54d1a2bb957a430212b1f2b1c88553878a (diff) | |
Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 94487d4041..e91592b242 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4244,8 +4244,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { if (Opc == ISD::SIGN_EXTEND_INREG) { ExtType = ISD::SEXTLOAD; ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); - if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) - return SDValue(); } else if (Opc == ISD::SRL) { // Another special-case: SRL is basically zero-extending a narrower value. ExtType = ISD::ZEXTLOAD; @@ -4255,6 +4253,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { ExtVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() - N01->getZExtValue()); } + if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) + return SDValue(); unsigned EVTBits = ExtVT.getSizeInBits(); |