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authorOwen Anderson <resistor@mac.com>2010-07-18 08:47:54 +0000
committerOwen Anderson <resistor@mac.com>2010-07-18 08:47:54 +0000
commit3ecdfafe3b06844ab0412b48f6daedf3e13e7037 (patch)
tree174bd64b9e3a9186d57fdf2de7a6c2dc5babe300 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent12f35c52a533da0c2c4c3e0a04f83355514992f9 (diff)
Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108639 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e671752464..271b2b621d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4926,6 +4926,19 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
Tmp, N0.getOperand(1));
}
+
+ // (f32 fp_round (f64 sqrt (f64 fp_extend (f32)))) -> (f32 sqrt)
+ EVT VT0 = N0.getValueType();
+ if (VT == MVT::f32 &&
+ N0.getOpcode() == ISD::FSQRT && VT0 == MVT::f64) {
+ SDValue N1 = N0.getOperand(0);
+ EVT VT1 = N1.getValueType();
+ if (N1.getOpcode() == ISD::FP_EXTEND && VT1 == MVT::f64 &&
+ N1.getOperand(0).getValueType() == MVT::f32) {
+ return DAG.getNode(ISD::FSQRT, N->getDebugLoc(), MVT::f32,
+ N1.getOperand(0), N->getOperand(1));
+ }
+ }
return SDValue();
}