diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-10-12 20:23:19 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-10-12 20:23:19 +0000 |
| commit | 3657ffe03733cf7cd9d6ed823ad696edb4547362 (patch) | |
| tree | d6a0a6e61fb893a408f2330b6268d557b631e003 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 494cec6e5888ee8dc697f95f0806813fb0f08a57 (diff) | |
add a minor dag combine noticed when looking at PR945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2c15f39db4..70ff8371f7 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1664,6 +1664,13 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); } + // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign + // bit, which is unmodified by sra. + if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { + if (N0.getOpcode() == ISD::SRA) + return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); + } + // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). if (N1C && N0.getOpcode() == ISD::CTLZ && N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { |