Compile this:

        xori r6, r2, 1
        rlwinm r6, r6, 0, 31, 31
        cmpwi cr0, r6, 0
        bne cr0, LBB1_3 ; endif

to this:

        rlwinm r6, r2, 0, 31, 31
        cmpwi cr0, r6, 0
        beq cr0, LBB1_3 ; endif


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26047 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 853dc1420d..05c487c98d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2544,6 +2544,32 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
                             DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 
                                             ExtDstTy),
                             Cond);
+      } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
+                 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+                 (N0.getOpcode() == ISD::XOR ||
+                  (N0.getOpcode() == ISD::AND && 
+                   N0.getOperand(0).getOpcode() == ISD::XOR &&
+                   N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
+                 isa<ConstantSDNode>(N0.getOperand(1)) &&
+                 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
+        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We can
+        // only do this if the top bits are known zero.
+        if (TLI.MaskedValueIsZero(N1, 
+                                  MVT::getIntVTBitMask(N0.getValueType())-1)) {
+          // Okay, get the un-inverted input value.
+          SDOperand Val;
+          if (N0.getOpcode() == ISD::XOR)
+            Val = N0.getOperand(0);
+          else {
+            assert(N0.getOpcode() == ISD::AND && 
+                   N0.getOperand(0).getOpcode() == ISD::XOR);
+            // ((X^1)&1)^1 -> X & 1
+            Val = DAG.getNode(ISD::AND, N0.getValueType(),
+                              N0.getOperand(0).getOperand(0), N0.getOperand(1));
+          }
+          return DAG.getSetCC(VT, Val, N1,
+                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
+        }
       }
       
       uint64_t MinVal, MaxVal;