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| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-03 07:21:16 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-03 07:21:16 +0000 |
| commit | 1a854be35295fd1c9c4d0d0f8894e720e22b5e4f (patch) | |
| tree | d78033451bfdc4a2f69408ad56aa8f24825b7f62 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | b8f4e0aa1719c1d5b93b096a8723ec7f68b4929a (diff) | |
Rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31413 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b85a6b7c12..74e92218e5 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -187,7 +187,7 @@ namespace { SDOperand BasePtr; SDOperand Offset; ISD::MemOpAddrMode AM = ISD::UNINDEXED; - if (TLI.getLegalPreIndexedAddressBase(N, BasePtr, Offset, AM, DAG)) { + if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) { // Try turning it into a pre-indexed load / store except when // 1) Another use of base ptr is a predecessor of N. If ptr is folded // that would create a cycle. |