Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor

some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 1 deletions

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index b6bc44e849..06d8ed9b25 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -50,7 +50,7 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
       assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
       std::vector<SUnit *> &UseList = Uses[Reg];
       SUnit *&Def = Defs[Reg];
-      // Optionally add output and anti dependences
+      // Optionally add output and anti dependences.
       if (Def && Def != SU)
         Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
                      /*PhyReg=*/Reg, Cost);
@@ -102,6 +102,15 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
   }
 }
 
+void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
+  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
+
+  // Compute the latency for the node.  We use the sum of the latencies for
+  // all nodes flagged together into this SUnit.
+  SU->Latency =
+    InstrItins.getLatency(SU->getInstr()->getDesc().getSchedClass());
+}
+
 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
   SU->getInstr()->dump();
 }