misched: DAG builder must special case earlyclobber

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 0 deletions

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index e2f33aa735..ed85963cc8 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -442,6 +442,15 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
   SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
   LiveInterval *LI = &LIS->getInterval(Reg);
   VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
+
+  // Special case: An early-clobber tied operand reads and writes the
+  // register one slot early. e.g. InlineAsm.
+  //
+  // FIXME: Same special case is in shrinkToUses. Hide under an API.
+  if (SlotIndex::isSameInstr(VNI->def, UseIdx)) {
+    UseIdx = VNI->def;
+    VNI = LI->getVNInfoBefore(UseIdx);
+  }
   // VNI will be valid because MachineOperand::readsReg() is checked by caller.
   MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
   // Phis and other noninstructions (after coalescing) have a NULL Def.