diff options
| author | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:12 +0000 |
| commit | 5e920d7c83c20474fc3470209869978628ccf8da (patch) | |
| tree | 338319ef98616a63d15a3b93c2109dd20190dd7c /lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | e9ef4ed13ba84ef27da831afa27b7955c8f09530 (diff) | |
misched: Added ScheduleDAGInstrs::IsPostRA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index a6556a51c8..c9255b04da 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -33,9 +33,10 @@ using namespace llvm; ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, - const MachineDominatorTree &mdt) + const MachineDominatorTree &mdt, + bool IsPostRAFlag) : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), - InstrItins(mf.getTarget().getInstrItineraryData()), + InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag), Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT), FirstDbgValue(0) { DbgValues.clear(); @@ -253,7 +254,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { unsigned Reg = MO.getReg(); if (Reg == 0) continue; - assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); + assert(!IsPostRA || TRI->isPhysicalRegister(Reg) && + "Virtual register encountered!"); // Optionally add output and anti dependencies. For anti // dependencies we use a latency of 0 because for a multi-issue |