diff options
author | Chris Lattner <sabre@nondot.org> | 2008-01-07 07:27:27 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2008-01-07 07:27:27 +0000 |
commit | 749c6f6b5ed301c84aac562e414486549d7b98eb (patch) | |
tree | 275f34b73cd0673d5e8fdcfe02cdb6d60c5422c2 /lib/CodeGen/RegisterScavenging.cpp | |
parent | 682b8aed0779ac0c9a6a13d79ccc1cff3e9730cf (diff) |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 758c6c14a0..aeed72cef5 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -92,10 +92,11 @@ void RegScavenger::forward() { } MachineInstr *MI = MBBI; + const TargetInstrDesc &TID = MI->getDesc(); // Reaching a terminator instruction. Restore a scavenged register (which // must be life out. - if (MI->getDesc()->isTerminator()) + if (TID.isTerminator()) restoreScavengedReg(); // Process uses first. @@ -122,7 +123,6 @@ void RegScavenger::forward() { setUnused(ChangedRegs); // Process defs. - const TargetInstrDescriptor *TID = MI->getDesc(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isRegister() || !MO.isDef()) @@ -134,7 +134,7 @@ void RegScavenger::forward() { continue; } // Skip two-address destination operand. - if (TID->findTiedToSrcOperand(i) != -1) { + if (TID.findTiedToSrcOperand(i) != -1) { assert(isUsed(Reg) && "Using an undefined register!"); continue; } @@ -152,13 +152,13 @@ void RegScavenger::backward() { MachineInstr *MI = MBBI; // Process defs first. - const TargetInstrDescriptor *TID = MI->getDesc(); + const TargetInstrDesc &TID = MI->getDesc(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isRegister() || !MO.isDef()) continue; // Skip two-address destination operand. - if (TID->findTiedToSrcOperand(i) != -1) + if (TID.findTiedToSrcOperand(i) != -1) continue; unsigned Reg = MO.getReg(); assert(isUsed(Reg)); |