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authorEvan Cheng <evan.cheng@apple.com>2008-11-18 22:56:19 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-11-18 22:56:19 +0000
commit63a431c6704e711713b0258bd987cfb257767cf4 (patch)
treea9e350b5998d44a76f723ff52bed3920aabdc10e /lib/CodeGen/RegisterScavenging.cpp
parent9c64bf3905ea338719800008c03d95a17cb26689 (diff)
We also need to keep the operand index for two address check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59562 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r--lib/CodeGen/RegisterScavenging.cpp20
1 files changed, 11 insertions, 9 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index a7bb17dc84..e89b2a09c9 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -193,25 +193,25 @@ void RegScavenger::forward() {
bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
// Separate register operands into 3 classes: uses, defs, earlyclobbers.
- SmallVector<const MachineOperand*, 4> UseMOs;
- SmallVector<const MachineOperand*, 4> DefMOs;
- SmallVector<const MachineOperand*, 4> EarlyClobberMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.getReg() == 0)
continue;
if (MO.isUse())
- UseMOs.push_back(&MO);
+ UseMOs.push_back(std::make_pair(&MO,i));
else if (MO.isEarlyClobber())
- EarlyClobberMOs.push_back(&MO);
+ EarlyClobberMOs.push_back(std::make_pair(&MO,i));
else
- DefMOs.push_back(&MO);
+ DefMOs.push_back(std::make_pair(&MO,i));
}
// Process uses first.
BitVector UseRegs(NumPhysRegs);
for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
- const MachineOperand &MO = *UseMOs[i];
+ const MachineOperand MO = *UseMOs[i].first;
unsigned Reg = MO.getReg();
if (!isUsed(Reg)) {
@@ -244,7 +244,9 @@ void RegScavenger::forward() {
for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
const MachineOperand &MO = (i < NumECs)
- ? *EarlyClobberMOs[i] : *DefMOs[i-NumECs];
+ ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
+ unsigned Idx = (i < NumECs)
+ ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free.
@@ -254,7 +256,7 @@ void RegScavenger::forward() {
}
// Skip two-address destination operand.
- if (TID.findTiedToSrcOperand(i) != -1) {
+ if (TID.findTiedToSrcOperand(Idx) != -1) {
assert(isUsed(Reg) && "Using an undefined register!");
continue;
}