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authorJakob Stoklund Olesen <stoklund@2pi.dk>2009-08-06 21:19:03 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2009-08-06 21:19:03 +0000
commit31f5591c91d4c012901018013aba19b0015fa6a0 (patch)
treef3cd28690b0820283c2412a7cfc635574b2d5d28 /lib/CodeGen/RegisterScavenging.cpp
parentbceda93251ff2cbcf54fb315e23027f426bfea80 (diff)
Get rid of RegScavenger::backwards() before the bitrot spreads.
If we need it one day, there is nothing wrong with putting it back in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78337 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r--lib/CodeGen/RegisterScavenging.cpp64
1 files changed, 0 insertions, 64 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index c3e03ab676..79ea579492 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -294,70 +294,6 @@ void RegScavenger::forward() {
}
}
-void RegScavenger::backward() {
- assert(Tracking && "Not tracking states!");
- assert(MBBI != MBB->begin() && "Already at start of basic block!");
- // Move ptr backward.
- MBBI = prior(MBBI);
-
- MachineInstr *MI = MBBI;
- DistanceMap.erase(MI);
- --CurrDist;
-
- // Separate register operands into 3 classes: uses, defs, earlyclobbers.
- SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
- SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
- SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
- continue;
- if (MO.isUse())
- UseMOs.push_back(std::make_pair(&MO,i));
- else if (MO.isEarlyClobber())
- EarlyClobberMOs.push_back(std::make_pair(&MO,i));
- else
- DefMOs.push_back(std::make_pair(&MO,i));
- }
-
-
- // Process defs first.
- unsigned NumECs = EarlyClobberMOs.size();
- unsigned NumDefs = DefMOs.size();
- for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
- const MachineOperand &MO = (i < NumDefs)
- ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
- unsigned Idx = (i < NumECs)
- ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
- if (MO.isUndef())
- continue;
-
- // Skip two-address destination operand.
- if (MI->isRegTiedToUseOperand(Idx))
- continue;
-
- unsigned Reg = MO.getReg();
- assert(isUsed(Reg));
- if (!isReserved(Reg))
- setUnused(Reg, MI);
- }
-
- // Process uses.
- BitVector UseRegs(NumPhysRegs);
- for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
- const MachineOperand MO = *UseMOs[i].first;
- unsigned Reg = MO.getReg();
- assert(isUnused(Reg) || isReserved(Reg));
- UseRegs.set(Reg);
-
- // Set the sub-registers as "used".
- for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- UseRegs.set(SubReg);
- }
- setUsed(UseRegs);
-}
-
void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
if (includeReserved)
used = ~RegsAvailable;