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authorOwen Anderson <resistor@mac.com>2008-01-01 21:11:32 +0000
committerOwen Anderson <resistor@mac.com>2008-01-01 21:11:32 +0000
commitf6372aa1cc568df19da7c5023e83c75aa9404a07 (patch)
tree9cc85598bdfe4e6af602fffcca57f03c61c0dc3f /lib/CodeGen/RegAllocSimple.cpp
parent80fe5311b5e9e5c4642ff46ba2377173c17797f6 (diff)
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index a60c63c28e..7ea9623303 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -144,7 +144,8 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumLoads;
- MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@@ -152,11 +153,13 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
}