diff options
| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2003-12-14 13:24:17 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2003-12-14 13:24:17 +0000 |
| commit | 4d7af65903cbc858464362e70a6adf499982ec8a (patch) | |
| tree | 5f40fb851e4f08c9aa8ebe952bb876ccb02c2ffb /lib/CodeGen/RegAllocSimple.cpp | |
| parent | 97323a47d88315b98e5ac38d64ba2a9e3f02b501 (diff) | |
Change interface of MachineOperand as follows:
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 202123ad10..44f37c61e8 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -184,13 +184,13 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.opIsDefOnly() || op.opIsDefAndUse()) { + if (op.isDef()) { if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot assert(MI->getOperand(1).isRegister() && MI->getOperand(1).getAllocatedRegNum() && - MI->getOperand(1).opIsUse() && + MI->getOperand(1).isUse() && "Two address instruction invalid!"); physReg = MI->getOperand(1).getAllocatedRegNum(); |