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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-19 06:19:09 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-19 06:19:09 +0000
commit2acef2da068763d7a48934de96a2fbef440beee5 (patch)
treec255b752aeeaa763b62cfa0915bf823250881f04 /lib/CodeGen/RegAllocSimple.cpp
parent04319bb2bda50d2ae7cc284cb1c4e742b44a466b (diff)
Rename reloads/spills to loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index b1726efddc..68f09d0505 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -28,8 +28,8 @@
using namespace llvm;
namespace {
- Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
- Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+ Statistic<> NumStores("ra-simple", "Number of stores added");
+ Statistic<> NumLoads ("ra-simple", "Number of loads added");
class RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
@@ -130,7 +130,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
- ++NumReloaded;
+ ++NumLoads;
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@@ -142,7 +142,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
- ++NumSpilled;
+ ++NumStores;
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}