Change interface of MachineOperand as follows:

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 6 deletions

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 4a3eb110c8..425c9d42d4 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -507,7 +507,9 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // to be live-in, or the input is badly hosed.
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if (MI->getOperand(i).opIsUse() && MI->getOperand(i).isVirtualRegister()){
+      if (MI->getOperand(i).isUse() &&
+          !MI->getOperand(i).isDef() &&
+          MI->getOperand(i).isVirtualRegister()){
         unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
         unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
         MI->SetMachineOperandReg(i, PhysSrcReg);  // Assign the input register
@@ -541,8 +543,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // Loop over all of the operands of the instruction, spilling registers that
     // are defined, and marking explicit destinations in the PhysRegsUsed map.
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if ((MI->getOperand(i).opIsDefOnly() ||
-           MI->getOperand(i).opIsDefAndUse()) &&
+      if (MI->getOperand(i).isDef() &&
           MI->getOperand(i).isPhysicalRegister()) {
         unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
         spillPhysReg(MBB, I, Reg, true);  // Spill any existing value in the reg
@@ -565,8 +566,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // we need to scavenge a register.
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse())
-          && MI->getOperand(i).isVirtualRegister()) {
+      if (MI->getOperand(i).isDef() &&
+          MI->getOperand(i).isVirtualRegister()) {
         unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
         unsigned DestPhysReg;
 
@@ -585,7 +586,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
           // This maps a = b + c into b += c, and saves b into a's spot
           assert(MI->getOperand(1).isPhysicalRegister()  &&
                  MI->getOperand(1).getAllocatedRegNum() &&
-                 MI->getOperand(1).opIsUse() &&
+                 MI->getOperand(1).isUse() &&
                  "Two address instruction invalid!");
           DestPhysReg = MI->getOperand(1).getAllocatedRegNum();