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| author | Chris Lattner <sabre@nondot.org> | 2006-03-25 23:00:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-25 23:00:56 +0000 |
| commit | c8e2c5561c65d048198c211baae9e5b961799767 (patch) | |
| tree | 4208042a60dc1d62616b9cc8e64abf5f2755e7f0 /lib/CodeGen/RegAllocLinearScan.cpp | |
| parent | c985d828bc4cf63348b74a8a9fbd8c1b6809dbb0 (diff) | |
Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27133 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 252fcfc2e8..59467c1e0f 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -539,6 +539,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur) DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n"); + // Find a register to spill. float minWeight = float(HUGE_VAL); unsigned minReg = 0; for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), @@ -549,6 +550,9 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur) minReg = reg; } } + + // If we didn't find a register that is spillable, try aliases? + // FIXME: assert(minReg && "Didn't find any reg!"); DEBUG(std::cerr << "\t\tregister with min weight: " << mri_->getName(minReg) << " (" << minWeight << ")\n"); |