diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2011-01-27 07:26:15 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-01-27 07:26:15 +0000 |
| commit | adf9c8b0e7e7365a172e3c452dfe108f31d9a387 (patch) | |
| tree | ad167371e73ffca0af9a3a26eec04ca1cb0ba499 /lib/CodeGen/RegAllocLinearScan.cpp | |
| parent | f382f3b4dd047a8e60371c6642d1d5a2358d3eb1 (diff) | |
Avoid modifying the OneClassForEachPhysReg map while iterating over it.
Linear scan regalloc is currently assuming that any register aliased with
a member of a regclass must also be in at least one regclass. That is not
always true. For example, for X86, RIP is in a regclass but IP is not.
If you're unlucky, this can cause a crash by invalidating the iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 14f672666d..b959878bcd 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -431,8 +431,12 @@ void RALinScan::ComputeRelatedRegClasses() { for (DenseMap<unsigned, const TargetRegisterClass*>::iterator I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end(); I != E; ++I) - for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) - RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]); + for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) { + const TargetRegisterClass *AliasClass = + OneClassForEachPhysReg.lookup(*AS); + if (AliasClass) + RelatedRegClasses.unionSets(I->second, AliasClass); + } } /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try |