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authorEvan Cheng <evan.cheng@apple.com>2007-11-04 08:32:21 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-11-04 08:32:21 +0000
commit9aeaf7593bb3c124aa8a5aa9623efcf3db3b0534 (patch)
tree179d7756302812b510015cd7b5ff65b29aee8b24 /lib/CodeGen/RegAllocLinearScan.cpp
parent03e6c7091e1b6f37d6ba55ad3ee1c2cba10ec8e4 (diff)
If an interval is being undone clear its preference as well since the source interval may have been undone as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43670 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 2d675b09b7..98b62cee31 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -209,7 +209,7 @@ void RALinScan::ComputeRelatedRegClasses() {
/// different register classes or because the coalescer was overly
/// conservative.
unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
- if (cur.preference && cur.preference == Reg || !cur.containsOneValue())
+ if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
return Reg;
VNInfo *vni = cur.getValNumInfo(0);
@@ -791,6 +791,11 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
vrm_->clearVirt(i->reg);
unhandled_.push(i);
}
+
+ // It interval has a preference, it must be defined by a copy. Clear the
+ // preference now since the source interval allocation may have been undone
+ // as well.
+ i->preference = 0;
}
// Rewind the iterators in the active, inactive, and fixed lists back to the