diff options
author | Jim Laskey <jlaskey@mac.com> | 2006-11-07 12:25:45 +0000 |
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committer | Jim Laskey <jlaskey@mac.com> | 2006-11-07 12:25:45 +0000 |
commit | 7902c75331fa8f38fc8380f5573d935c0d149ef5 (patch) | |
tree | 720e42ebcf35dbe1899efdce48ba2e1de7a11e47 /lib/CodeGen/RegAllocLinearScan.cpp | |
parent | a7bb6498fec20c9d0f7cfce4f7df7f6852ad1d57 (diff) |
Use correct value for float HUGH_VAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31500 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index d8d838d34f..2aea512b16 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -545,7 +545,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur) DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n"); // Find a register to spill. - float minWeight = float(HUGE_VAL); + float minWeight = HUGE_VALF; unsigned minReg = 0; for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), e = RC->allocation_order_end(*mf_); i != e; ++i) { @@ -582,7 +582,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur) // if the current has the minimum weight, we need to spill it and // add any added intervals back to unhandled, and restart // linearscan. - if (cur->weight != float(HUGE_VAL) && cur->weight <= minWeight) { + if (cur->weight != HUGE_VALF && cur->weight <= minWeight) { DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';); int slot = vrm_->assignVirt2StackSlot(cur->reg); std::vector<LiveInterval*> added = |