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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-12-17 23:16:35 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-12-17 23:16:35 +0000
commitaf24964251e27c2dd863239ba66ffd967b593be5 (patch)
tree6aa2aad96c4ee1e25e25a227c37a5c0230d1a022 /lib/CodeGen/RegAllocGreedy.cpp
parentf428eb6c1b09a2322b7a577b0bf2e49dd107bcea (diff)
Make the -verify-regalloc command line option available to base classes as
RegAllocBase::VerifyEnabled. Run the machine code verifier in a few interesting places during RegAllocGreedy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122107 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
-rw-r--r--lib/CodeGen/RegAllocGreedy.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index d8c1b3d4da..8dbb56809b 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -328,6 +328,9 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit)
.splitAroundLoop(Loop->getLoop());
+ if (VerifyEnabled)
+ MF->verify(this);
+
// We have new split regs, don't assign anything.
return 0;
}
@@ -400,6 +403,9 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
+ if (VerifyEnabled)
+ MF->verify(this);
+
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
DomTree = &getAnalysis<MachineDominatorTree>();
ReservedRegs = TRI->getReservedRegs(*MF);