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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
| commit | 17c836c4b51a14f07a5d5442cf2e984474a8f57d (patch) | |
| tree | 74181d3329eae68c0137d0d18c5ce2db3ff901fe /lib/CodeGen/ProcessImplicitDefs.cpp | |
| parent | c84f975e6fa65049ecd3268f830218e791893efd (diff) | |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ProcessImplicitDefs.cpp')
0 files changed, 0 insertions, 0 deletions