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author | Duncan Sands <baldrick@free.fr> | 2010-11-10 13:00:08 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2010-11-10 13:00:08 +0000 |
commit | b2cbdc35ba85c04df15b0e991d9be371691ab08c (patch) | |
tree | d7df0dda287bfbce6408f6c5f742863fe933d5af /lib/CodeGen/MachineSSAUpdater.cpp | |
parent | 46cf7c5fd6768f94d8938458668672a54d710f6d (diff) |
Simplify binary operations where one operand is a select instruction.
The simplifications performed here never create new instructions, they
only return existing instructions (or a constant), and so are always a
win. In theory they should transform (for example)
%z = and i32 %x, %y
%s = select i1 %cond, i32 %y, i32 %z
%r = and i32 %x, %s
into
%r = and i32 %x, y
but in practice they get into a fight with instcombine, and lose.
Unfortunately instcombine does a poor job in this case. Nonetheless
I'm committing this transform to make it easier to discuss what to
do to make peace with instcombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118679 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineSSAUpdater.cpp')
0 files changed, 0 insertions, 0 deletions