diff options
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-09-16 15:18:53 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-09-16 15:18:53 +0000 |
| commit | 8c6936a58b75d7d185014839ea95377eb2fbd878 (patch) | |
| tree | b1c3b13698a605df8f2ff77c1c28ec2911d24ff0 /lib/CodeGen/MachineInstr.cpp | |
| parent | 1318bed20c52792913405c0d41766f69829cf944 (diff) | |
Dump routine now writes out allocated register numbers if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3737 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index d3608c1320..e12922e4c8 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -112,8 +112,8 @@ MachineInstr::dump() const cerr << " " << *this; } -static inline std::ostream &OutputValue(std::ostream &os, - const Value* val) +static inline std::ostream& +OutputValue(std::ostream &os, const Value* val) { os << "(val "; if (val && val->hasName()) @@ -122,6 +122,12 @@ static inline std::ostream &OutputValue(std::ostream &os, return os << (void*) val << ")"; // print address only } +static inline std::ostream& +OutputReg(std::ostream &os, unsigned int regNum) +{ + return os << "%mreg(" << regNum << ")"; +} + std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr) { os << TargetInstrDescriptors[minstr.opCode].opCodeString; @@ -165,14 +171,17 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop) case MachineOperand::MO_VirtualRegister: os << "%reg"; OutputValue(os, mop.getVRegValue()); + if (mop.hasAllocatedReg()) + os << "==" << OutputReg(os, mop.getAllocatedRegNum()); break; case MachineOperand::MO_CCRegister: os << "%ccreg"; OutputValue(os, mop.getVRegValue()); + if (mop.hasAllocatedReg()) + os << "==" << OutputReg(os, mop.getAllocatedRegNum()); break; case MachineOperand::MO_MachineRegister: - os << "%reg"; - os << "(" << mop.getMachineRegNum() << ")"; + OutputReg(os, mop.getMachineRegNum()); break; case MachineOperand::MO_SignExtendedImmed: os << (long)mop.immedVal; |
