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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-06-07 20:53:48 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-06-07 20:53:48 +0000 |
| commit | bdcae3825633082774ec702fd05cc556ed683ca6 (patch) | |
| tree | 5eec0d8e82dc4363e0d84da6e5b9dde423fbabb4 /lib/CodeGen/MachineDominators.cpp | |
| parent | 2f6622c7bf10b07ab1370b3696d334bd91d7091d (diff) | |
Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates.
This may happen on MIC devices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineDominators.cpp')
0 files changed, 0 insertions, 0 deletions