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| author | Dan Gohman <gohman@apple.com> | 2009-04-13 15:22:29 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-04-13 15:22:29 +0000 |
| commit | 70f2f65aacdbc96fe158b2860b5f0bad075ee548 (patch) | |
| tree | 11daa6afcb2bd27b872172eb4b3891cd1708d73a /lib/CodeGen/LiveIntervalAnalysis.cpp | |
| parent | 9a77a92859b609a767d65b91ac7eb86a1a3ae680 (diff) | |
Don't abort on an aliasing physical register that does not have
a live interval. This is needed for some upcoming subreg changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68956 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LiveIntervalAnalysis.cpp')
| -rw-r--r-- | lib/CodeGen/LiveIntervalAnalysis.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 3bc05a9b9a..7c8041b169 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -2235,7 +2235,7 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, // If there are registers which alias PhysReg, but which are not a // sub-register of the chosen representative super register. Assert // since we can't handle it yet. - assert(*AS == SpillReg || !allocatableRegs_[*AS] || + assert(*AS == SpillReg || !allocatableRegs_[*AS] || !hasInterval(*AS) || tri_->isSuperRegister(*AS, SpillReg)); bool Cut = false; |