aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen/LiveIntervalAnalysis.cpp
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2010-04-28 23:52:26 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-04-28 23:52:26 +0000
commit6691a8935c9f2e049ff5eed45ba2894f60108909 (patch)
tree3e9b6b0e6ee05b1ecd5cab5a9f0724787066cd1a /lib/CodeGen/LiveIntervalAnalysis.cpp
parentf38c6c89f1137f54adb76bb375b15ff0ec3a925a (diff)
- Really preserve dbg_value instructions when the register is spilled.
- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LiveIntervalAnalysis.cpp')
-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index bd8a54cc22..7a2feeacab 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1297,11 +1297,12 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
++ri;
if (MI->isDebugValue()) {
// Modify DBG_VALUE now that the value is in a spill slot.
- if (Slot == VirtRegMap::NO_STACK_SLOT) {
+ if (Slot != VirtRegMap::MAX_STACK_SLOT || isLoadSS) {
uint64_t Offset = MI->getOperand(1).getImm();
const MDNode *MDPtr = MI->getOperand(2).getMetadata();
DebugLoc DL = MI->getDebugLoc();
- if (MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot,
+ int FI = isLoadSS ? LdSlot : (int)Slot;
+ if (MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, FI,
Offset, MDPtr, DL)) {
DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
ReplaceMachineInstrInMaps(MI, NewDV);