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authorEvan Cheng <evan.cheng@apple.com>2009-06-13 09:12:55 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-06-13 09:12:55 +0000
commite7d6df73530a98a5cc5f69ddfd17073b464caa57 (patch)
tree2ee5d1bb7677ae95573303bdc8a19a2e96866f82 /lib/CodeGen/LLVMTargetMachine.cpp
parentdaf9e02893e7e17ca2267ffd5e994f824adbb624 (diff)
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LLVMTargetMachine.cpp')
-rw-r--r--lib/CodeGen/LLVMTargetMachine.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index b3c60e6393..a163cac75b 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -240,7 +240,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
PM.add(createMachineSinkingPass());
- printAndVerify(PM, /* allowDoubleDefs= */ true);
+ printAndVerify(PM, /* allowDoubleDefs= */ false);
}
// Run pre-ra passes.